As semiconductor memory technology progresses, increasing device density continues to be critical. Increasing device density may be achieved by scaling the memory cell. Alternatively, multiple bits can be store in each memory cell. For example, two bits can be stored in a multiple level cell MLC) utilizing four threshold levels. An un-programmed cell has a minimum threshold value determined by fabrication parameters (e.g., core implant doping level). The minimum threshold value is typically utilized to represent the two-bit combination of ‘11’; a first threshold value represents the combination ‘10’; a second threshold value represents the combination ‘01’; and a third threshold value represents the combination ‘00’. Similarly, three bits can be stored in a multiple level cell utilizing eight threshold levels, and so on.
Referring to FIG. 1A, a multiple level cell (MLC) 105 according to the conventional art is shown. As depicted in FIG. 1A, the MLC 105 is fabricated about a semiconductor substrate 110. The MLC 105 comprises a source region 115 and a drain region 120. A channel region 125 is disposed between the source region 115 and the drain region 120. A floating gate 130 is formed above the channel region 125. A first isolating layer 135 is disposed between the floating gate 130 and the channel region 125. A control gate 140 is formed above the floating gate 130. A second isolating layer 145 is disposed between the control gate 140 and the floating gate 130.
The voltage on the control gate 140 must first exceed a threshold voltage before appreciable current flows between the source and drain regions. Thereafter, the current is specified by the following equation:1=K/L(VG−VT)Where K is a constant, L is the channel length of the MLC, VG is the voltage on the control gate 140, and VT is the threshold voltage. From the above equation it is appreciated that the current is proportional to the voltage on the control gate 140 less the threshold voltage. Hence, the state of one or more bits can be represented by adjusting the threshold voltage level. The threshold voltage can be adjusted by injecting charge onto the floating gate 130. The state of the bits are then determined by the magnitude of the current flowing between the source region 115 and the drain region 120.
Typically, reading the MLC 105 entails applying a positive voltage (e.g., 5 Volts (V)) to the control gate 140, and a positive voltage (e.g., 1V) to the drain region 120. The source region 115 and substrate 110 are grounded. The drain current is then compared to a plurality of reference currents to determine the state of the MLC 105.
Erasing the MLC 105, in one configuration, entails applying a positive voltage (e.g., 5V) to the source region 115, a negative voltage (e.g., −10V) to the control gate 140, and tri-stating (e.g., high impedance) the drain region 120. The large potential difference between the control gate 140 (e.g., −10V) and the source region 115 (e.g., 5V) causes electrons trapped on the floating gate 130 to be repelled by the control gate 140 and attracted by the source region 115. The electrons tunnel from the control gate 130 through the first insulating layer 135 to the source 115.
In another configuration, erasing the MLC 105 entails applying a large positive voltage (e.g., 10V) to the source region 115, grounding the control gate 140, and tri-stating (e.g., high impedance) the drain region 120. The large potential difference between the control gate 140 (e.g., 0V) and the source region 115 (e.g., 10V) causes electrons trapped on the floating gate 130 to be attracted by the source region 115. The electrons tunnel from the control gate 130 through the first insulating layer 135 to the source region 115.
Programming the MLC 105 typically entails applying a positive voltage (e.g., 8.5V) to the control gate 140, a positive voltage (e.g., 5V) to the drain region 120, while grounding the source region 115 and substrate 110. The potential difference between drain region 120 and source region 115, causes electrons to flow across the channel from the source region 115 (e.g., 0V) toward the drain region (e.g., 5V). The high voltage applied to the control gate 140 causes some electrons to overcome the potential barrier of the first insulating layer 135. Thus, electrons are injected into the floating gate 130. The injected electrons on the floating gate 130 act to increase the threshold voltage of the MLC 105. The amount of injected electrons on the floating gate 130 determines the value of the threshold voltage.
In order to program multiple bits on a single cell, multiple threshold levels must be programmed. Referring now to FIG. 2A, a graphical representation of the correlation between the state of two bits and four threshold levels, according to the conventional art, is shown. As depicted in FIG. 2A, the bit combination of ‘11’ is represented by an un-programmed cell (e.g., VT=VT MIN=1V). The bit combination of ‘10’ is represented by a first threshold voltage, VT1 (VT1=1V). The bit combination of 01 is represented by a second threshold voltage, VT2 (VT2=5V). The bit combination of ‘00’ is represented by a third threshold voltage, VT3 (VT3=7V). The plurality of threshold voltage levels are spread out between the minimum threshold voltage and the maximum threshold voltage that can be programmed and erased for a given memory device.
Referring now to FIG. 2B, a graphical representation of the correlation between the state of three bits and eight threshold levels, according to the conventional art, is shown. As depicted in FIG. 2B, the bit combination of ‘111’ is represented by an un-programmed cell (e.g., VT=VT MIN=1V). The bit combinations of ‘110’-‘000’ are represented by the respective threshold voltages, VT1−VT7 (e.g., VT1=2V, VT2=3V, VT3=4V, VT4=5V, VT5=6V, VT6=7V, and VT7=8V).
The multiple threshold levels can be provided for by adjusting the length of time that the programming voltages are applied to the cell. However, manufacturing process variations result in some cells programming faster than other cells. A fast cell will have a higher threshold voltage than a slow cell, for a given programming period. Similarly, variations in the actual voltage levels used for programming will result in some cells being programmed faster than other cells. As a result, the threshold cannot be set perfectly. Therefore, each threshold voltage will have a statistical distribution.
Referring now to FIG. 3, a graphical representation of the statistical deviation of multiple programmed threshold voltage levels according to the conventional art is shown. As depicted in FIG. 3, a multiplicity of desired threshold voltages (e.g., VT=1V, 3V, 5V, 7V; and VT=VT MIN=1V) are shown. Each actual programmed threshold value will have a certain distribution 305, between a plurality of cells of a memory device. However, to ensure reliable operation of the memory device, the distribution 305 of a given threshold level must be separated from the next higher or lower threshold voltage level by a specified margin 310. The larger the deviation of a given threshold voltage level, the smaller the margin 310 is between adjacent threshold levels. Therefore, the distribution 305 in programming a desired threshold value needs to be minimized. However, simply controlling the length of time that programming voltages are applied to the cell does not provide sufficient control of the distribution 305 of threshold values, to provide reliable operation of the memory device.
One solution, according to the conventional art, is to apply a plurality of short programming pulses and performing a verify cycle between each programming pulse. Referring now to FIG. 4, a method of programming a MLC according to the conventional art is shown. As depicted in FIG. 4, the process begins with applying a programming pulse, at step 410. For example, an 8.5V pules is applied to a control gate, a 5V pulse is applied to a drain, while grounding a source and substrate of the MLC. The length of the pulse is some fraction (e.g., 1/20th) of the average time required to program a first threshold value.
Next at step 415, a program verify is performed after application of each program pulse. The program verify typically comprises reading the memory cell. For example, 5V is applied to the control gate, 1V is applied to the drain region, while the source region and substrate are grounded. The drain current is then compared to a reference current corresponding to the desired threshold voltage.
Next at step 420, if the drain current is less than the reference current, another program pulse is applied followed by another program verify. Additional programming pulses and program verify steps are performed until the drain current is substantially equal to the reference current corresponding to the desired threshold voltage. When the drain current is substantially equal to the reference current, the programming of the cell is complete.
Referring now to FIG. 5, a timing diagram of gate, drain, and threshold voltages in a MLC being programmed, according to the conventional art is shown. As depicted in FIG. 5, a threshold voltage 505 (e.g., Vt2=5V) of a MLC is programmed. The threshold voltage 505 gradually rises from a minimum threshold voltage (e.g., VT MIN=1V) to threshold voltage 505 (e.g., Vt2=5V). A series of voltage pulses 510 (e.g., Vg=8.5V) are applied to a gate, while another series of voltage pulses 515 (e.g., 5V) are applied to a drain of the MLC. Between each set of voltage pulses 520, 525, a verify process 530 is performed to determine the current threshold level.
Each set of voltage pulse 520, 525 increases the threshold voltage 505 by a fraction of the total desired threshold voltage. A fast programming MLC will reach the same threshold voltage 505 with fewer pulses 520, 525. A slower programming MLC will require more programming pulses 520, 525 to reach the same threshold voltage 505. By utilizing multiple sets of voltage pulses 520, 525, the variation in threshold voltages 505 between cells will be less than or equal to the incremental increase resulting from one set of voltage pulses 520. Therefore, reducing the width of the voltage pulse 520 reduces variations in the threshold voltage levels 505.
The multiple programming pulse method is disadvantageous in that the method results in a relatively long total programming time. The program verify takes a longer period of time than a programming pulse. Hence, every program verify significantly increases the total programming time. Furthermore, setup time between a programming pulse and a verify cycle and between the verify cycle and the next programming pulse is also incurred.